1. Field of the Invention
The present invention generally relates to methods and systems for classifying defects detected on a reticle. Certain embodiments relate to a method for assigning a classification to a defect detected on a reticle based on an impact that the defect will have on the performance of a device being fabricated on a wafer.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
The terms “reticle” and “mask” are used interchangeably herein. A reticle generally includes a transparent substrate such as glass, borosilicate glass, and fused silica having patterned regions of opaque material formed thereon. The opaque regions may be replaced by regions etched into the transparent substrate. Many different types of reticles are known in the art, and the term reticle as used herein is intended to encompass all types of reticles.
The layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. The polygons can be generally defined by their size and placement on the reticle. Each reticle is used to fabricate one of the various layers of the device being fabricated on the wafer. The layers of a device such as an integrated circuit (IC) may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
In particular, the reticle is used to pattern a resist in a lithography process step, and then the patterned resist is used to form features of devices on the wafer. Therefore, the patterned features that are formed on a reticle and are to be transferred to the wafer reflect the characteristics of the features that are included in the device design. In other words, the features that are formed on the reticle are based on and used to form individual components of the device. The complexity of the device design, therefore, has a direct impact on the manufacture and inspection of reticles. In particular, as the complexity of device designs increases, successful reticle manufacture becomes more difficult. For instance, as the dimensions of the device features and the spacings between the features decrease, the dimensions and spacings of features on the reticle also decrease. In this manner, it becomes more difficult to form these features on a reticle due to, for example, limitations of the reticle manufacturing process. In addition, as is known in the art, the difficulty of successfully reproducing these features on wafers increases as the dimensions and spacings decrease.
Due to the important role that reticles play in semiconductor fabrication, ensuring that the reticles have been manufactured satisfactorily (such that the reticles can be used to produce the desired images on wafers) is critical to successful semiconductor fabrication. For example, defects in reticles are a source of yield reduction in device manufacturing. Therefore, inspection of a reticle is a critical step in reticle manufacturing processes. In general, during a reticle inspection process, an image of the reticle is typically compared to a baseline image. The baseline image is either generated from the circuit pattern data or from an adjacent die on the reticle itself. Either way, the image features are analyzed and compared with corresponding features of the baseline image. Each feature difference may then be compared against a threshold value. If the image feature varies from the baseline feature by more than the predetermined threshold, a defect may be defined. Once a reticle is fabricated and inspected, it may be qualified as acceptable for manufacturing and released to manufacturing.
Although conventional reticle inspections provide adequate levels of detection accuracy for some applications, other applications require a higher sensitivity or lower threshold value (for identifying defects) while other applications require less stringent, higher threshold levels. Accordingly, some inspection methods have been developed that inspect reticles with varying stringency based on the intent of the device designer. Examples of such methods are illustrated in commonly owned U.S. Pat. No. 6,529,621 to Glasser et al. and U.S. Pat. No. 6,748,103 to Glasser et al., which are incorporated by reference as if fully set forth herein. In this manner, decisions as to the appropriate stringency that should be used to detect defects on reticles can be made based on the electrical significance of features in the reticle layout data.
Such methods have substantially improved the accuracy, meaningfulness, usefulness, and throughput of reticle inspection. However, such methods do not take into account a number of other variables that can be used to further increase the value of reticle inspection. For example, there are potentially many defects on a reticle that have little bearing on the performance or yield of the chip. These defects consume resources in the form of operator review time involved in determining the importance of a defect and potentially in reticle repair time or effective yield (i.e., post-repair yield) of the reticle manufacturing process. If the defect does not have a real impact on the chip yield or the chip performance, then those resources are not being efficiently deployed. Furthermore, if a reticle defect is unrepairable and yet will print on an active area of the wafer, then the reticle is currently discarded. If it can be determined that the defect does not have a performance impact on the chip, then the reticle could be used thereby saving both time and money. However, historically, reticle inspection has not considered final circuit performance on either the inspection sensitivity or defect classification.
Accordingly, it would be advantageous to develop methods and systems for classifying defects detected on a reticle based on the impact that the defects will have on the performance of a device being fabricated on a wafer thereby increasing the efficiency of reticle defect review and repair, increasing the effective yield of the reticle manufacturing process, and decreasing the cost and time associated with reticle manufacturing.